forked from brl/citadel
20 lines
766 B
Diff
20 lines
766 B
Diff
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The ISB instruction isn't available in ARMv5 or v6, so
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guard it's use to fix the build on qemuarmv5.
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Upstream-Status: Pending
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Signed-off-by: Ross Burton <ross.burton@arm.com>
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diff --git a/js/src/jit/arm/Architecture-arm.cpp b/js/src/jit/arm/Architecture-arm.cpp
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--- a/js/src/jit/arm/Architecture-arm.cpp 2024-01-18 17:31:32.078718197 +0000
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+++ b/js/src/jit/arm/Architecture-arm.cpp 2024-01-18 18:00:16.738921445 +0000
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@@ -529,7 +529,9 @@
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void FlushExecutionContext() {
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#ifndef JS_SIMULATOR_ARM
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+#if __ARM_ARCH >= 7
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// Ensure that any instructions already in the pipeline are discarded and
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// reloaded from the icache.
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asm volatile("isb\n" : : : "memory");
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+#endif
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#else
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// We assume the icache flushing routines on other platforms take care of this
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